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PIC16F627A/628A/648A

DS40044G-page 144

2009 Microchip Technology Inc.

17.6

Timing Diagrams and Specifications

FIGURE 17-4:

EXTERNAL CLOCK TIMING

TABLE 17-4:

EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No.

Sym

Characteristic

Min

Typ

Max

Units

Conditions

FOSC

External CLKIN Frequency(1)

—

MHz XT and RC Osc mode,

VDD = 5.0 V

—

MHz HS, EC Osc mode

—

200

kHz LP Osc mode

Oscillator Frequency(1)

—

MHz RC Osc mode, VDD = 5.0V

0.1

—

MHz XT Osc mode

—

200

MHz

kHz

HS Osc mode

LP Osc mode

—

MHz INTOSC mode (fast)

—

kHz INTOSC mode (slow)

1TOSC

External CLKIN Period(1)

250

—

XT and RC Osc mode

—

HS, EC Osc mode

5—

—

μsLP Osc mode

Oscillator Period(1)

250

—

RC Osc mode

250

—

10,000

XT Osc mode

—

1,000

HS Osc mode

5—

—

μsLP Osc mode

—

250

—

INTOSC mode (fast)

—21

—

μs

INTOSC mode (slow)

2TCY

Instruction Cycle Time

200

TCY

TCY = 4/FOSC

3TosL,

TosH

External CLKIN (OSC1) High

External CLKIN Low

100*

—

XT oscillator, TOSC L/H duty

cycle

External Biased RC

Frequency

10 kHz*

—

4 MHz

—

VDD = 5.0V

These parameters are characterized but not tested.

Data in “Typ” column is at 5.0V, 25

°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

Note 1:

Instruction cycle period (TCY) equals four times the input oscillator time-based period. All specified values

are based on characterization data for that particular oscillator type under standard operating conditions

with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-

ation and/or higher than expected current consumption. All devices are tested to operate at “Min” values

with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max” cycle time

limit is “DC” (no clock) for all devices.

OSC1

CLKOUT

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